Integrated circuits are the backbone of computers and most modern consumer electronics. In a typical integrated circuit fabrication, various semiconductor materials are formed into ingots generally comprised of nearly pure silicon, then sliced into wafers. Each wafer is typically processed through deposition, removal, patterning, and/or modification of electrical properties such that a plurality of chips are formed on the wafer. Both the chips and the wafers are delicate, so after deposition, removal, patterning, and/or modification of electrical properties is complete, the chips are singulated from the wafer and packaged.
Despite advances in technology and power systems, integrated circuits often experience anomalous inputs (typically called “transients”), whether on power, input, output, or input/output (“I/O”) pins, that can cause unexpected functionality, errors, failure, or even destruction of components of integrated circuits. These transients generally include electrostatic discharge, voltage spikes, voltage drops, current spikes, current drops, electromagnetic radiation, and other electrical noise. Integrated circuits are generally designed to withstand some amount of these transients such that the transients neither produce erroneous results nor cause failure of the integrated circuit. Typical integrated circuits include one or more internal transient protection circuits that attempt to reduce or eliminate the effects of transients on the integrated circuit. However, these transient protection circuits may fail, and thus it is often desirable to determine the response of chips, wafers, and/or other electronic devices to transients before packaging. As such, wafer testing is often used after various processing steps to test the response of the wafer and/or chip to transients, such as electrostatic discharge.
In conventional wafer testing, probe cards typically contact a few contact points to test the wafer, a chip, or more generally the integrated circuit (“IC”). Conventional probe cards may include up to about twenty-five probes to touch the contact points of the IC, though conventional wafer testing systems only send signals to one or two contact points. Conventional wafer testing systems utilize a signal generator and ground connection located remotely from the probe card and connected to the probe card through a bundle of wires. Thus, in conventional wafer testing systems, a transient, such as an electrostatic discharge signal, may travel about fourteen inches across a coaxial cable, while a path for the transient to return to ground may travel about twenty-five inches and also across a coaxial cable. Therefore, the signal from the signal generator typically traverses the cable to the probe card, is relayed through the probe card to a first contact point, proceeds through the IC to a second contact point, is relayed from the second contact point to the probe card, is relayed through the probe card to the cable, and is finally relayed through the cable to the remotely located ground.
As such, conventional wafer testing systems use signal generators and ground connections that are generally remote from the probe card. Thus, an electrostatic discharge signal often traverses a coaxial cable, which, due to the typically long length thereof, results in great variations in waveform shape of the signal, loss of energy in the signal, and induces variant signals. Thus, conventional wafer systems that perform wafer-level electrostatic discharge tests are typically limited to providing a signal of about 4,000 volts. Furthermore, the path to ground from the IC generally proceeds along a separate coaxial cable than the coaxial cable that carries the electrostatic discharge signal. As such, the path to ground is generally as long, if not longer, than the path traveled by the electrostatic discharge signal. Additionally, the path to ground is generally confined to the small cross-section of the coaxial cable. Thus, a magnetic field may build up on one, or both, of the coaxial cables, and inductance cables may cause a substantial back voltage, which may further prevent an adequate electrostatic discharge to the probe card, or an adequate return to ground from the probe card. As such, conventional wafer testing systems often experience deleterious effects based upon their configuration.
Moreover, conventional wafer-level testing systems are usually inefficient at testing more than one set of contact points of the IC quickly and efficiently. For example, wafer-level testing may require that multiple electrostatic discharge signals be sent to various contact points of the IC. Thus, conventional wafer-level testing systems typically require that the probe card move to, and thus make contact with, multiple areas of the IC in succession. However, it is well known that typical ICs, such as chips and wafers, are extremely delicate. In fact, typical chips and wafers are generally no more than 800 micrometers thick. Thus, conventional wafer-level testing systems often have to contact and re-contact an IC many times, vastly increasing the chance of accidental destruction of the IC. Moreover, conventional wafer-level testing systems configured to contact up to about twenty-five contact points are typically rewired when those systems are required to test more than one or two contact points of the IC, thus expending time and money associated with that rewiring. Furthermore, some conventional testing systems forego the rewiring, and instead include a plurality of wafer-level testing systems and are typically configured to test the IC in succession, with each of the plurality of wafer-level testing systems contacting various subsets of the plurality of contact points of the device. However, this also expends significant time and money, as multiple wafer-level testing systems must be bought, configured, and set up in an assembly format, not to mention the time expended configuring the IC in each testing system.
Consequently, there is a continuing need to improve wafer-level testing of an integrated circuit, and particularly a continuing need to test the integrated circuit with a wafer-level testing system that alleviates the problems inherent in conventional wafer-level testing systems.